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version 1.2 august 1, 2006 preliminary information (subject to change) FXS50LD1-03 databook high-drive line driver (ld) for the fx100100s-5 multi-mode (vdsl2, vdsl, adsl2+, adsl2, adsl) sle chipset application: fttx subscriber located equipment (sle)
? 2006 ikanos communications, inc. all rights reserved. ii version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential 47669 fremont boulevard fremont ca 94538 united states of america (usa) 1.510.979.0400 (phone) 1.510.979.0500 (facsimile) www.ikanos.com ? 2006 ikanos communications, inc. all rights reserved. ikanos communications, ikanos, the ikanos logo, smartleap, cleverconnect, ikanos programmable operating system, fx, fxs, vlr and fiber fast are among the trademarks or registered trademarks of ikanos communications. all other trademarks mentioned herein are properties of their respective holders. this product and related documentation are protected by co pyright and distributed under licenses restricting, without limitation, its use, reproduction, copying, distribution, and decompilation. no part of this product or related documentation may be reproduced in any form by any means electronic, mechanical, magnetic, optical, manual, or otherwise, without prior written authorization of an authorized offi cer of ikanos communications, inc (ikanos). disclaimer the information in this book is furnished for informational us e only, is subject to change wi thout notice, and should not be construed as a commitment by ikanos. ikanos assumes no responsibility or liability for any errors or inaccuracies that may appear in this book. ikanos makes no representations or warranties with respect to the design and documentation herein described and especially disclaims any implied warranties of merchantability or fitness fo r any particular purpose. further, ikanos reserves the right t o revise the design and associated documentation and to make chan ges from time to time in the content without obligation of ikanos to notify any person of such revisi ons or changes. use of this document does not convey or imply any license under patent or other rights. ikanos does not authorize the use of its products in life-support system s where a malfunction or failur e may result in injury to the user. a manufacturer that uses ik anos products in life-support app lications assumes all the risks o f doing so and indemnifies ikanos against all charges. document status the document status is shown on the bottom of each page. this describes the status of information in this document, which can be one of: advance ?information on a product in early development. preliminary ?current information on a product under development. final ?complete information on a developed product.
? 2006 ikanos communications, inc. all rights reserved. iii preliminary information (subject to change) - ikanos confidential version 1.2 august 1, 2006 revision history version date changes 1.0 june 06, 2006 first release. 1.1 june 16, 2006 updated package type in part number. 1.2 august 1, 2006 updated the following: ? ?thermal resistance? on page 10 . ? chapter 6, ??ordering information?? to include ?marking data? .
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table of contents v version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 1 overview about the fx100100s-5 chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features of the fx100100s-5 chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 about FXS50LD1-03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 FXS50LD1-03 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 sample target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 single port hostless sle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 residential gateway with internal voip dsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 chapter 2 pin definition FXS50LD1-03 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 chapter 3 functional description block diagram of the FXS50LD1-03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 4 electrical data operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 low noise amplifier (lna) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bandgap bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chapter 5 mechanical data chapter 6 ordering information marking data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 fab vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 assembly vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 part status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table of contents
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list of figures vii version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. figure 1?1 sample single port hostless (vdsl2/vdsl/adsl2+/adsl) sle . . . . . . . . . . . . . . . . . . . 4 figure 1?2 sample residential gateway with internal voip dsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2?1 FXS50LD1-03 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3?1 block diagram of the FXS50LD1-03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 5?1 top view of 7 x 7 x 1.4 mm 32-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5?2 dimensions of 7 x 7 x 1.4 mm 32-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6?1 FXS50LD1-03 part number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 list of figures
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list of tables ix version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. table 2?1 FXS50LD1-03 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4?1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4?2 themal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4?3 electrical specifications ? line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4?4 electrical specifications?lna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4?5 bandgap bias specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6?1 marking specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6?2 fab vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6?3 assembly vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6?4 part status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 list of tables
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1 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 1 overview 1.1 about the fx100100s-5 chipset the fx100100s-5 chipset is a single-port, standards-compliant solution that enables equipment vendors to develop high-perform ance subscriber located equipment (sle) such as modems, bridges, routers, voip gateways, and residential gateways. since this chipset is highly programmable with superior integration features, it can be easily customized for worldwide applicatio ns. sle vendors can therefore build fewer products, reduce time to market, an d dramatically lower development, manufacturing, and inventory costs. the fx100100s-5 chipset consist of the following components: ? burst mode engine (bme)?fxs50bm1-00, which is a single-port digital signal processing (dsp) engine. ? integrated front end (ife)?fxs50if1-03, which includes adc, dac, filters, and amplifiers. ? high-drive line driver (ld)?FXS50LD1-03, which is a single port 14.5dbm line driver across 30 mhz bandwidth. 1.1.1 features of the fx100100s-5 chipset the fx100100s-5 chipset ships with the following features: ? industry leading performance ? one port of asymmetric line data rates up to 100 mbps downstream and up to 100 mbps upstream ? one port of symmetric line data rates up to 100 mbps ? universal sle ? vdsl2, vdsl, adsl2+, adsl ? lower bom and board space ? one design worldwide 100/100 + vlr ? simplified vlr filter ? ip or atm with a single design ? integrated aal5 sar
2 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 1. overview FXS50LD1-03 databook ? compliant with the following worldwide standards: ? itu-t g.993.2 (vdsl2) ? itu-t g.993.1-2004 (vdsl) ? ansi t1.424-2004 ? etsi ts 101 270-1 and ts 101 270-2 ? g.992.x (adsl2+, adsl2, adsl) ? flexibility to be deployed for a variety of markets: ? fiber to the exchange (fttx)? fttp, ftth, fttb, and fttc ? multi-tenant and multi-dwelling unit (mxu) ? exceptional programmability: ? real time optimization of dedi cated data and voice bandwidth. ? programmable throughput in increments of 64 kbps that enables service levels in tiers. ? drive level up to 14.5dbm. ? faster deployment and easier integr ation with any other equipment using ikanos programmable operating system (ipos): ? ipos consists of opti mized firmware and os/ p independent api commands. ? ipos lets vendors configure the chipset for fttx/ mxu asymmetric/ symmetric applications and atm/ethern et protocols with scalable speeds. ? standards-compliant dmt mo dulation and frequency division multiplexing (fdm). ? spectrally compatible with pots and isdn for voice services. ? support for hostless ethernet bridge modem and any hostful application. ? backward compatible with sl8100, sl8800, sl94xx, fx7030, fx10050, fx100100, and fx100100-4 chipsets. ? industrial operating temperature of ?40 to +85 c. 1.2 about FXS50LD1-03 the FXS50LD1-03 is a single-port 100100 differential line driver that extends the reach and transmission reliability of sle equipment. the FXS50LD1-03 is a part of the fx100100s-5 multi-mode sle chipset and integrates all the features required to deploy a line interface for fttx subscriber located equipment (sle). a transformer connects the FXS50LD1-03 to the line. on the network side, the FXS50LD1-03 is connected to the fxs50if1-03.
chapter 1. overview FXS50LD1-03 databook 3 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. 1.2.1 FXS50LD1-03 features the FXS50LD1-03 contains the following features: ? compact single-port line driver th at delivers 14.5dbm transmit power. ? complies with the following worldwide standards: ? itu-t g.993.2 vdsl2 standard ? itu-t g.993.1-2004 vdsl standard ? ansi t1.424-2004 ? etsi ts 101 270-1 and ts 101 270-2 ? itu-t g.992.x (adsl2+, adsl2, adsl) standards ? targeted at subscriber loca ted equipment (sle) such as: ? hostless bridge modem ? hostful residential gateway ? low operating power: ? dynamically reduces power when using less bandwidth ? low power operation: +12v and +2.5v power supply. ? integrated 2-bit low noise amplifier (lna) with gain and bias control. ? integrates all negative and positive feedback comp onents excluding sense resistors. ? analog echo cancellation system to canc el transmit signals in the receive path. ? integrated prog rammable hybrid. ? integrated serial interface. ? integrated bandgap reference generator. ? integrated tertiary lightning protection. ? packaged in 7x7 mm 32-pin lqfp. ? industrial operating temperature of ?40 to +85 c. ? 30 mhz bandwidth.
4 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 1. overview FXS50LD1-03 databook 1.3 sample target applications 1.3.1 single port hostless sle figure 1?1 shows an example of a hostless single port sle that can be built using the fx100100s-5 chipset. the external prog ram memory (sdram) and boot flash memory store the firmware and power up the system respectively. figure 1?1 sample single port hostless (vdsl2/vdsl/adsl2+/adsl) sle 1.3.2 residential gateway with internal voip dsp figure 1?2 shows an example of a residential gateway hostful sle that can be built using the fx100100s-5 chipset. fxs50bm1 -00 interfaces with the fusiv network processor through the utopia or xmii interface. the fusiv network processor provides the processing power required for the residential gateway networking function. figure 1?2 sample residential gateway with internal voip dsp fxs50bm1 bme fxs50ld1 ld xmii flash (hostless) sdram ethernet phy txfmr fxs50if1 ife line fxs50bm1 sdram flash mii five-port ethernet switch usb 2.0 host peripheral fxs50if1 ddr dsp fusiv network processor security engine qos tdm codec slic slic pci wlan, mpeg,... mini-pci connector uart bluetooth fxs50ld1 sdram line fx100100s-5 txfmr telephone xmii
5 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 2 pin definition 2.1 FXS50LD1-03 signals figure 2?1 FXS50LD1-03 pinout diagram FXS50LD1-03 txip txin rxgnd rxop rxon rxgnd rxvcc lvdd 1 2 3 4 5 6 7 8 txop txon rxgnd rxip rxin hcnp hcnn rxvcc 32 31 30 29 28 27 26 25 txgnd txvcc ldvcc ldgnd ldvcc txsp txsn ldgnd 9 10 11 12 13 14 15 16 sc1 lvss sc2 sc3 sc4 rxgnd exr rxgnd 24 23 22 21 20 19 18 17
6 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 2. pin definition FXS50LD1-03 databook ta b l e 2 ? 1 FXS50LD1-03 signals pin # signal name signal type description 1 txip input tx positive input 2 txin input tx negative input 3rxgndinput rx ground 4 rxop output rx positive output 5 rxon output rx negative output 6rxgndinput rx ground 7 rxvcc input rx power supply 8 lvdd input logic power supply 9 sc1 input serial interface clk1 10 lvss input logic ground 11 sc2 input serial interface clk2 12 sc3 input serial interface data 13 sc4 input test pin (normally lvss) 14 rxgnd input rx ground 15 exr output bias external pin 16 rxgnd input rx ground 17 rxvcc input rx power supply 18 hcnn input hybrid negative input 19 hcnp input hybrid positive input 20 rxin input rx negative input 21 rxip input rx positive input 22 rxgnd input rx ground 23 txon output tx negative output 24 txop output tx positive output 25 ldgnd input ld ground 26 txsn input positive feed back negative input 27 txsp input positive feed back positive input 28 ldvcc input ld power supply 29 ldgnd input ld ground 30 ldvcc input ld power supply 31 txvcc input tx power supply 32 txgnd input tx ground
7 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 3 functional description 3.1 block diagram of the FXS50LD1-03 figure 3?1 shows the function block diagram of the single-port FXS50LD1-03. the various function blocks on the fxs50ld1 -03 are described in the sections below. figure 3?1 block diagram of the FXS50LD1-03 line driver amplifier (includes all gain and feedback components) control logic bias reference programmable hybrid receiver amp line tx rx ld bias external set resistor rbt rbt n
8 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 3. functi onal description FXS50LD1-03 databook 3.2 functional summary the FXS50LD1-03 consists of a line driv er, a low-noise receive amplifier, and programmable hybrid circuits. the FXS50LD1-03 transmit path includes the line driver, which combines high speed and high power delivery capability (u p to 14dbm) with low power dissipation. the line driver provides external bias setti ng resistor that conf igures the internal bandgap biasing with accurate quiescent cu rrent setting and with power flexibility the FXS50LD1-03 receive path includes the low noise amplifier (lna), and the programmable hybrid network.
9 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 4 electrical data voltages should be applied to the fx100100s-5 multi-mode sle chipset in the following order: 1. 12v to the ld i/o circuitry 2. 2.5v to the se rial interface note: make sure the FXS50LD1-03 conforms to the following power-up requirement: the 12v powers up first and the 2.5v powers up next. 4.1 operating conditions operating conditions refer to the limits that guarantee the functi oning of the device. functioning of the device is guar anteed using the following methods: ? production testing between 0c and 70c ? characterization and periodic sampling of production units between ?40c and +85c ta b l e 4 ? 1 operating conditions parameter typical value unit number of chan nels (ports) 1 power supply voltage note : the power supply voltage can be between 5% of the typical values. +12 v power dissipation : ? 14.5dbm output power on the line <1w mw/port ? lna mw/port ? serial interface and hybrid mw/port operating temperature range ?40 to +85 c transformer turns ratio 1:1.5
10 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 4. electrical data FXS50LD1-03 databook 4.2 thermal resistance 4.3 electrical specifications 4.3.1 line driver 4.3.2 low noise amplifier (lna) ta b l e 4 ? 2 themal resistance package conditions ja (junction to ambient) jb (junction to ball) jc (junction to case) unit 7 7mm 32-pin lqfp still air (0m/s air flow) 52.0 na 15.74 oc/w ta b l e 4 ? 3 electrical specifications ? line driver parameter typical value unit gain (excluding transformer) 20/17 db hd3 (f=2 mhz, rl=44.4 ohm, vout=1/2 peak swing voltage) note: only the differential hd3 of the FXS50LD1-03 is tested. 60 dbc input referred noise 12 nv/ hz ta b l e 4 ? 4 electrical specifications?lna parameter typical values unit hd3 (vout=1/2 peak swing voltage) at 2 mhz 60 dbc maximum output swing 3 vppd output current drive tbd ma power dissipation tbd mw
chapter 4. electrical data FXS50LD1-03 databook 11 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. 4.4 bandgap bias ta b l e 4 ? 5 bandgap bias specifications parameter typical value unit vbg voltage 1.22 v temperature variation note: the temperature varies between ?40c to +85c. 3 % external resistor note: the external resistor is added to ensure high-power performance tbd
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13 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 5 mechanical data all dimensions in figure 5?1 are in millimeters. figure 5?1 top view of 7 x 7 x 1.4 mm 32-pin lqfp 3 2 top view
14 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 5. mechanical data FXS50LD1-03 databook figure 5?2 dimensions of 7 x 7 x 1.4 mm 32-pin lqfp 1 2 1 3
15 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 6 ordering information figure 6?1 FXS50LD1-03 part number in figure 6?1 : ? FXS50LD1-03-a0-ql0-l is part of the fx100100s -5 chipset that supports vdsl2 profiles 8a/8b/8c/8d, 12a/12b, 17a, and 30a. ? * refers to the environmental parameter, where: ? 0 corresponds to standard package ? 1 corresponds to lead free package ? 2 corresponds to green package fx s 50 ld 1 - 03 - a0 - ql* 0 - l chipset family: fx (fibre extension) chipset type: s (ont/subscriber located equipment) generation chipset function: ld (line driver) # of ports performance: 03 (100/100 mbps) chip revision package type: ql (lqfp) environmental parameter: 0 (leaded package) operating temperature: l (industrial ?40 to +85c)
16 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. chapter 6. orderi ng information FXS50LD1-03 databook 6.1 marking data 6.1.1 fab vendor code ta b l e 6 ? 1 marking specification line # marking specification example(s) 1 logo 2 part number ? fxo51bm8- ? ikf6836-a0- 3 package ? a0-hb0 ? pb1-c 4 datacode tap0522: see table 6?2 , table 6?3 , and table 6?4 for legends on fab vendor code, assembly vendor code, and part status respectively. 5 fab lot number fab lot number ta b l e 6 ? 2 fab vendor code foundry code designator tsmc t umc u ibm b chartered c tower w ams a
chapter 6. ordering information FXS50LD1-03 databook 17 version 1.2 august 1, 2006 preliminary information (subject to change) - ikanos confidential ? 2006 ikanos communications, inc. all rights reserved. 6.1.2 assembly vendor code 6.1.3 part status samsung s imp m ta b l e 6 ? 3 assembly vendor code assembly vendor code designator asek a spil l statschippac-singapore s ose o statschippac-china h statschippac-korea r utac u amkor?philippines p amkor?singapore g asem m asecl c ta b l e 6 ? 4 part status part status code designator production p engineering e marketing sample m ta b l e 6 ? 2 fab vendor code (continued) foundry code designator
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